HW4 computer mass production in Q4 2021

[diplomat33]

"Tesla is working on HW4.0 self-driving chip with semiconductor company TSMC with a timeline for mass production in Q4 2021, according to a new report coming out of China."

"Mass production wouldn’t happen until Q4 2021 – meaning that we aren’t likely to see those chips inside Tesla production vehicles until 2022."

Tesla is working on HW 4.0 self-driving chip with TSMC for mass production in Q4 2021, report says - Electrek

So it looks like we are about 2 years away from the next gen FSD computer (HW4) getting into Tesla cars.

 

[WashingtonDCeV]

Now wondering if HW3 is replaceable to realize the promise of FSD; brand new Mode Y with FSD.

 

[J1mbo]

Pretty much in line with expectation then?

 

[Saghost]

Now wondering if HW3 is replaceable to realize the promise of FSD; brand new Mode Y with FSD.

I’ll be very surprised if it isn’t replaceable; the only way that’s likely is if HW4 includes additional sensors, and even then they’d likely be able to upgrade the computer itself.

But Tesla is currently convinced that isn’t necessary for FSD, and if they deliver all their promises with HW3, they might not offer an upgrade even if the hardware is capable of it.

 

[glide]

I’ll be very surprised if it isn’t replaceable; the only way that’s likely is if HW4 includes additional sensors, and even then they’d likely be able to upgrade the computer itself.

But Tesla is currently convinced that isn’t necessary for FSD, and if they deliver all their promises with HW3, they might not offer an upgrade even if the hardware is capable of it.

3.0 wont be capable of FSD. Just like 1.0, 2.0, and 2.5, etc...

 

[CyberGus]

Maybe they'll deliver my CyberTruck my letting it drive itself to Louisiana and back.

 

[Mardak]

"Each 12-inch wafer can only be cut out. 25 chips."

Are we sure this isn't for Dojo? Currently HW3/FSD is 20mm x 13mm which would fit ~200 per 300mm wafer, and it's currently on a 14nm process. 25 chips per wafer would be around 50mm x 35mm, so the chip is roughly 8x larger including switch to 7nm process.

 

[diplomat33]

"Each 12-inch wafer can only be cut out. 25 chips."

Are we sure this isn't for Dojo? Currently HW3/FSD is 20mm x 13mm which would fit ~200 per 300mm wafer, and it's currently on a 14nm process. 25 chips per wafer would be around 50mm x 35mm, so the chip is roughly 8x larger including switch to 7nm process.

It's possible that it is for Dojo. But then that would mean that Dojo is still 2 years away from going online? That seems like a long time.

 

[MP3Mike]

It's possible that it is for Dojo. But then that would mean that Dojo is still 2 years away from going online? That seems like a long time.

Why would it be two years away from going online if the chips would be in full production in just over a year? (And Elon recently said that Dojo is about a year out, which seems to line up.)

 

[TessP100D]

FSD is a LOOOOONG way away. No, it won’t be operating in your CT.

 

[diplomat33]

Why would it be two years away from going online if the chips would be in full production in just over a year? (And Elon recently said that Dojo is about a year out, which seems to line up.)

Well, the article says that the chips will enter mass production in Q4 2021. Then they need to be produce, shipped and assembled into Dojo. Ok not 2 years, more like 1.5 years.

 

[TessP100D]

The article? When Tesla finally installs this option in a real vehicle, that’s for sale to the public, that is when we will know. It’s a long ways away.

 

[DanCar]

No chance hardware 4 will do level 5. But hopeful it will do level 3 on limited access freeway.

3.0 wont be capable of FSD. Just like 1.0, 2.0, and 2.5, etc...

 

[DanCar]

The large chip size, only 25 chips per 12 inch wafer, suggests this is NOT hardware 4. More likely some version of dojo.

 

[DanCar]

The large chip size, only 25 chips per 12 inch wafer, suggests this is NOT hardware 4. More likely some version of dojo.

Tesla Hardware 3 (Full Self-Driving Computer) Detailed - AutoPilot Review
I would expect hardware 4 to be around the same size as current hardware 3 which is 260 millimeters square or 16 millimeters on one side. This chip is 40 millimeters on one side or 1,600 millimeters squared.
Die Per Wafer Calculator - CALY Technologies

 

[GrimRe]

The large chip size, only 25 chips per 12 inch wafer, suggests this is NOT hardware 4. More likely some version of dojo.

Its definitely for Dojo

• 25 chips per wafer is ludicrously low. Its either a typo or its part of the TSMC inFO_SoW manufacturing process. The inFO_SoW process mounts dies with separation to allow of in-wafer connectivity between dies. This would explain the low number of chips (although probably more to it)
  
  
• The cost per chip would be enormous and the power consumption waay outside the 90W TDP envelope for AutoPilot HW
  
  
• The benefit of wafer-scale fabrication is large improvements in interconnectivity, exactly what you want when running massive scale FP32 operations. This only makes sense for Dojo

TL;DR -- each chip will be 5-10x the transistor count than the NVIDIA A100, plus be transistor level optimised for FP32 operations... and Tesla have ordered thousands. Dojo will outperform the combined compute power of every single NVIDIA AI chip in operation across all the compute clouds globally. This is why Tesla needs to build Dojo as the alternative would be to take the entire public cloud compute and Amazon or Google etc wouldn't want this.

An A100 from NVIDIA has approx ~100 TF32 tera-op/s capacity. Elon has stated he wants a useful exaflop which would be million times higher.

 

[DanCar]

FP32 operations...

FP32 is a rookie mistake. They will later switch to int8 to optimize memory.

>benefit of wafer-scale fabrication is large improvements in interconnectivity
Suspect 80% of the chip is going to be sram.

 

[GrimRe]

FP32 is a rookie mistake. They will later switch to int8 to optimize memory.

>benefit of wafer-scale fabrication is large improvements in interconnectivity
Suspect 80% of the chip is going to be sram.

int8 for inference and fp32 for training is what I believe their strategy is. FP32 precision appears to bring much higher accuracy in RNNs such a long term driving policy planners.

 

[gluu]

From my own research, I believe this is HW4. InFO_SoW (Integrated Fan Out System on Wafer) from TSMC is a packaging system, the 7nm chips will still be standard sizes but packaged together on wafers which are likely 16nm/some high yield process.

TSMC to Build Supercomputing AI Chips, Ramps Wafer-Scale Computing - ExtremeTech

It seems this provides improved power efficiency over using a PCB.

The other wrinkle that the articles on HW4 mention that Broadcom is involved and the chip will be used for infotainment as well. I'm speculating that Broadcom is providing all the IP that sits around the AI processor, e.g. ARM cpus, ethernet NIC, wifi, etc. Previously they used Samsung IP and they're fabbing HW3 at Samsung, so that cannot carry over to TSMC.

Integrating the infotainment is interesting as well. I think this will provide several benefits:

1. The infotainment and autopilot systems are currently separate and I'm not sure what the cooling situation is, but this will simplify the cooling situation. Integrating the two will likely significantly reduce costs.
2. AI Chip capabilities will be available to infotainment. One obvious use is for really high quality voice recognition that can take advantage of the AI chip. Any application that sits in the infotainment will be able to use the AI chip I imagine, much like Apple's Neural Engine.
3. Sentry Mode currently runs through the Autopilot computer. I think integrating the infotainment here will make Sentry Mode more power efficient and more capable. I think of Sentry Mode as a lynchpin in Tesla's Insurance strategy, it should dramatically reduce insurance fraud and allow Tesla to price well below other providers based on that alone.

 

[GrimRe]

From my own research, I believe this is HW4. InFO_SoW (Integrated Fan Out System on Wafer) from TSMC is a packaging system, the 7nm chips will still be standard sizes but packaged together on wafers which are likely 16nm/some high yield process.

TSMC to Build Supercomputing AI Chips, Ramps Wafer-Scale Computing - ExtremeTech

It seems this provides improved power efficiency over using a PCB.

The other wrinkle that the articles on HW4 mention that Broadcom is involved and the chip will be used for infotainment as well. I'm speculating that Broadcom is providing all the IP that sits around the AI processor, e.g. ARM cpus, ethernet NIC, wifi, etc. Previously they used Samsung IP and they're fabbing HW3 at Samsung, so that cannot carry over to TSMC.

Integrating the infotainment is interesting as well. I think this will provide several benefits:

1. The infotainment and autopilot systems are currently separate and I'm not sure what the cooling situation is, but this will simplify the cooling situation. Integrating the two will likely significantly reduce costs.
2. AI Chip capabilities will be available to infotainment. One obvious use is for really high quality voice recognition that can take advantage of the AI chip. Any application that sits in the infotainment will be able to use the AI chip I imagine, much like Apple's Neural Engine.
3. Sentry Mode currently runs through the Autopilot computer. I think integrating the infotainment here will make Sentry Mode more power efficient and more capable. I think of Sentry Mode as a lynchpin in Tesla's Insurance strategy, it should dramatically reduce insurance fraud and allow Tesla to price well below other providers based on that alone.

It’s certainly possible. The thing I’m hung up on though is the 25 chips per wafer. This just makes no sense. Even if you use the largest common die size it’s still 125 per wafer.

If 25 chips is accurate then each chip would be several thousand dollars in part cost and require 500w of power. No way that would be for FSD or MCU.

Only explanation is typo or translation issue.