Elon stated the sort was for drive units: combined rotor, gears, and inverter.
A typical ST SiC 650V FET has a 25 C on resistance range of 18 to 26 mOhm. That is a 44% variation in internal dissipation for the same current level. Avoiding the edge requires designing to the worst case number vs nominal and thus derating the peak current/ peak torque/ peak power. By sorting/ testing/ binning, they can find the parts that are closer to nominal and get up to 20% more power from the inverter. Or, for the same power level, units that will produce 40% less heat (more laps around the track). They can also find parts better than nominal, for even more performance.
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I notice he says lot sorted, so it may be that STMicro is binning the SiC FETs at their factory (similar to LED suppliers) so the inverters have a known power level, then they double burn-in only those drive units.