Tesla Autonomous Driving H/W

[mongo]

It'll suck to be the pcb board designer troubleshooting timing issues

or it will be really awesome. (and suck for the chip team).

 

[BioSehnsucht]

Ya, that's one benefit of using your own designed asic and pcb. Instead of having pcie to send info in serial, you can just have a massive parallel bus with as many bits as you want to send info within 2 clock cycle.

At high bandwidths, multi-lane serial designs (such as PCIe, and similar) are much more feasible. Purely parallel data transmission becomes difficult the faster you do it as you have to keep the timing of all the parallel lines in sync. That's why nobody is building systems with "regular" PCI anymore, it's all PCI Express. A "single lane" PCIe 1.0 1x interface is already 250MB/s, vs 133MB/s for PCI (32-bit) at 33MHz (the common PCI configuration). You could get PCI-X (64-bit) at 66MHz at 533MB/s, or you could just add PCIe lanes or bump up to a more modern flavor of PCIe (2.0 1x: 500MB/s, 3.0 1x: 984.6MB/s). Modern PCIe has better round-trip latency as well.

There's really no point to inventing a new interface standard for the ASIC. Some form of PCIe is the most obvious choice.