so care to provide replacement commentary based on the rest of the post? Do you think the chip is slower/faster under certain (you decide) assumptions? Don't look too much into the NNs, those appear to be a straight compilation of regular production NNs they have (They clearly just compile it all from the same sources producign hw2, hw2.5 and now hw3 binaries), so we cannot conclude how the development branches go.
Without reading the post at all and only looking at just the picture. i just wanted to say that non-stacked convolution layers is pretty standard in the world of CNN nowadays, it all started with the first inception network from google which Google really showed that you don't have to just stack conv layers with pooling, drops, on top of each other, but that you can get clever with it. That and using smaller conv filters there is nothing mind blowing about it today. its pretty standard.
Here is Inception v1 from 2014
EDIT: After reading the post. My comments doesn't change. Only thing i would add is that I'm surprised people still take anything jimmy_d says seriously.
While I don't have the actual board to see what's running and what's not and it's possible the "a72 started" references are somewhat stale from previous revisions, I am 100% sure the exynos SoC is still in use because UFS, USB, I2C and PCIEx drivers are only present for that particular platform
Historically (hw2.5, mcu2) it's been 3-5 months from first appearances of such stuff in public firmwares to all cars on production line.
It's really easy to be a secret Tesla employee on the Internet where nobody asks for any proof
