Xavier is shipping now it appears

[BigD0g]

Time, to start looking out for HW3 I guess. Though, it's more the likely HW3 will be Tesla's own chip, but just in case it appears Xavier is shipping to customers in the very near future:

https://www.indiatimes.com/technolo...er-designed-for-self-driving-cars-337250.html

 

[Pale_Rider]

Sample end of Q1, production hopefully by the end of the year per his keynote last night. The really interesting board is their Pegasus board. One or two Xavier’s plus one or two P100 Volta discretes. Up to 320 DLTOPs compared to about roughly 10 DLTOPs for what is in our AP2 cars with single Pascal dGPUs. These are aimed at L5. Hopefully Tesla wasn’t that far off in their assessment of what is needed. Hard to say since these boards assume multiple Lidar inputs as well as camera. Time will tell, but at least I’ll get a free computer upgrade if I have the car that long, right? Lol

 

[Stoneymonster]

Sample end of Q1, production hopefully by the end of the year per his keynote last night. The really interesting board is their Pegasus board. One or two Xavier’s plus one or two P100 Volta discretes. Up to 320 DLTOPs compared to about roughly 10 DLTOPs for what is in our AP2 cars with single Pascal dGPUs. These are aimed at L5. Hopefully Tesla wasn’t that far off in their assessment of what is needed. Hard to say since these boards assume multiple Lidar inputs as well as camera. Time will tell, but at least I’ll get a free computer upgrade if I have the car that long, right? Lol

Remember, NVIDIA doesn’t exactly know what’s needed either, and they are building hardware to satisfy a bunch of different customers with different ideas on what sensor suite and NN power is required. They are going to keep adding more power and sensor inputs every year indefinitely. And every year Jen-Hsun is going to trot out on stage and explain why THIS new SoC is the one that will finally do level 5.

 

[lunitiks]

bet: xavier will never see a tesla. there will be custom soc

 

[Stoneymonster]

bet: xavier will never see a tesla. there will be custom soc

I doubt Tesla will do a full custom SoC. A dedicated NN ASIC, maybe. From a business perspective, I'd be very worried if they decided to become a CPU design house. (But I mostly agree with you on the Xavier front).

 

[Sertis]

I think they mentioned support for AR dash projection. Suppose that camera in the Model 3 would be for eye tracking?

 

[jimmy_d]

I doubt Tesla will do a full custom SoC. A dedicated NN ASIC, maybe. From a business perspective, I'd be very worried if they decided to become a CPU design house. (But I mostly agree with you on the Xavier front).

I've assumed that even if they do a SOC they won't develop the CPU IP themselves. I can see why Mobileye wanted a proprietary processor from a business model perspective, but I'm not clear on what upside that would have for Tesla, who is the end user as well as the IP provider.

I've gone back and forth on this SOC idea a bit. OTOH a dedicated NN chip can be extended to a full on SOC by just dropping on an ARM core, but that will definitely extend development time and it requires you to have your CPU requirements nailed down a couple of years before you ship. That seems kind of hard in a space as dynamic as the NN space is right now. So you save money and power and probably improve performance, but it comes at the cost of increased development risk and a longer delivery schedule. This seems like pretty much a standard SOC vs ASIC decision with the spin that usually the CPU is a big chunk of the real estate, whereas a systolic array type NN core probably ends up being a lot bigger than an ARM.

My general read is that power is not a huge issue for FSD compared to other embedded applications. The battery in the car is huge - you can pretty easily tolerate a couple of hundred watts during driving if it creates real value for the customer since it would only be a 1% change in range. Cost might be more of an issue, but keeping the Tegra and using the NN chip as a pure coprocessor is not a huge change to the BOM for the APE - especially if you're losing an Nvidia P106 as part of the deal. So that leaves performance as a potentially significant differentiator. The potential big win there is having a ton of bandwidth between your CPU and your NN accelerator. Having that huge bandwidth might let you simplify the NN accelerator since you can offload more stuff to the CPU. Or it might not - the design space is pretty complicated.

It feels to me like you'd want to build your first NN accelerator as a coprocessor with the intention of spinning it to pull in the CPU in generation 2. That seems to be what Google did with the TPU and it's a nice balance between time to market, risk, and performance. There's always a second rev and by the time they are ready to do that they'll know a lot more from experience with the first generation.