The conclusions in the article don't make sense to me, especially when they mention HPC chips in the article itself - HPC is datacenter, not in-car.
Only 25 chips from a 12" wafer at 7nm? That's probably a die size of over 400mm^2, maybe over 1000mm^2 depending on the assumptions you make about how good the yields are. That's as big or bigger than the largest high end GPU dies.
If 25 dies per 300mm (12") wafer are true, these are more likely chips for Dojo NN learning acceleration than chips for FSD HW NN in-car acceleration.
For comparison, HW 3.0 FSD chip is 20x13mm or 260mm^2, on 14nm node. On 7nm node, to be that much larger, would be an obscene number of transistors. A direct shrink from 14nm to 7nm would be roughly half the die area (in reality, nothing is a perfect scaling, it would be a bit bigger). So to be on the order of 3x~7x the transistor count (taking into consideration a smaller node and larger die area) would be nonsensical for FSD in-car hardware.
I suspect in their rush to be first to publish Electrek has made some incorrect assumptions.