OK. There's been a couple of derogatory comments about HW4 in here, mainly along the lines of, "Older cars won't get the upgrade!" and such. This is probably not the right thread, but there's a financial bit that may be of interest.
As a sometimes ASIC designer, I can report on this thing: The physically smaller an ASIC is, the better
yield one gets on ASIC production. On a given silicon wafer, the number of defects on the wafer has been (and continues to be) pretty much a constant. Bits of dust, problems with the crystalline lattice, etc.
So, yeah, build an ASIC that uses up an entire 8" wafer; the maximum yield might be considered to be 1 ASIC per wafer, which is truly not great. But the bigger problem is that the real yield will be Zero because of that background defect problem: That ASIC will have a bunch of defects on it that will kill it.
So, the better bet is to have gazillions of tiny little ASICs, the smaller the better, built on the wafer. Even before the diamond saw comes down and dices the wafer into individual ASICs, testing machines cometh down from on high and does a basic, "Does it work or not?" and puts (typically) a red dot on each dead one. So, if one has a 8" wafer with 1000 dies on it, one will end up with a dozen or two dead ones because of the defects, the rest will be fine.
Next: There's this metric, "line width", which is how narrow a feature one can etch into the semiconductor. What it also means: The smaller the line width, the
area of the transistor goes down by the square. Go from 10 nm to 5 nm, and, in the same area, one has
quadrupled the number of transistors one can put on the die.
Finally, there's the capacitance of those transistors. You'll have to take my word for it, but the capacitance of a transistor, which is proportional to the
area of the transistor, determines the speed of an ASIC, as well as its power dissipation. The general, back of the envelope calculation for power dissipation is
P = C*V*V
So, what happens when one gets a line width reduction? One can mess with things, but:
- If one keeps the same number of transistors in an ASIC, the yield goes up. Cost goes down.. lots.
- If one keeps the same number of transistors on an ASIC and runs at the same clock speed, the power dissipation drops. Lots. By the by: That improves reliability, since failure rates track with temperature.
- If one keeps the same number of transistors on an ASIC and runs the clock at the square of the difference in line widths, the power dissipation stays roughly the same, but one gets higher performance. At less cost.
In practice, if one is happy with the yield one is getting before the line shrink, one can build an ASIC with a quadruple number of transistors and, as a result, more complex functionality with roughly the same power dissipation. This is where Intel and AMD make their money.
If you're wondering, the stuff above is why Moore's Law works. (And, yeah, Moore's Law is slowing down these days, but isn't dead yet.)
Lots of choices for the engineer. But, during the latest earnings call, I listened to the question about retrofitting HW4 onto earlier cars, and if it was necessary to get FSD on the existing cars. Musk definitely hesitated, but stated that HW3 should be able to do the job.
And that's the point. The current driving computer, neural network processors and all, was designed back in 2018. It's 2022/2023 now, that's 4 or 5
years. Line widths have shrunk since 2018. This is Tesla: I wouldn't be surprised if HW4 has
some improvements in performance (well, they've been programming the baby, they probably have things they wanted fixed), but I'm betting they were looking for cheaper ASICs, lower power ASICs, probably by a factor of two or three, with increased performance a distant third place.
What this means: Reducing the cost of goods to build the car.
Not about needing it to get FSD to work.
Could be wrong, but doubt it.
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