Also there is something fishy about the reported new chip order from TSMC.
It has been widely reported as HW4, but it might not be so, it might actually be the Dojo chip we are speculating.
The news
article Ferragu replied to mentioned they use some kind of new “system on wafer” technique to directly build the whole system on wafers without base plate or PCB, then glue it to heat sinks.
A 12 inch wafers only yields 25 systems, and its 7nm.
That’s far too big of an area for next gen FSD computer. Also the order is for only 2000 waffles, so only 50k systems tops.
The news clearly referred to the chip as an HPC chip, not sure why people insist it would be the FSD computer for cars but not for backend data centers.
It also mentioned the chip was jointly designed by Broadcom and Tesla, to me that immediately sounds like the high speed switch fabric you would need for parallel training. I don’t remember HW3 was jointly developed with them, anyone heard anything different?
From what we heard(maybe not supposed to though) from autonomous day, HW4 would be more about iterating HW3 and make it cheaper and faster, I would expect lower costs and energy consumption, also performance improvements within 2x-10x, not the kind of big revolution if the new chip turns out to be HW4.
I don’t have enough knowledge about chips to say for sure, could someone who knows these staff comment on this?
(This is not OT, since implications of HW4 could have Osborne effects closer to its rumored release date. Also, I think Dojo is a much bigger deal for the future of the company than most people realized)