At least part of what he's saying makes sense, given the circuitry on the per-module management boards:
Think of it this way.. From the negative terminal of the entire pack to the positive terminal, there are sixteen modules, and let's say 400V for a nice round number. From the per-module BMB's perspective, there are negative (0v) and positive (~25v) ends. If you count from the pack negative, through module A, then module B, and so on until you reach the positive terminal, module A's negative is the pack negative, and mod A's positive is mod B's negative, and so on, in series. Clear?
Sorry, I know this is basic and well-understood, but bear with me. It's critical that everyone is up to speed on this much to make sense of what's next.
So, each BMB (per module) can bleed a group (a group of parallel cells) to equalize it with its (series) neighbors. It does this by shorting out that group's positive and negative ends (a difference of ~4v) through the bleeder resistor for that group. When you do this, you have at most 158R / 4 (paralleled resistance) = 39.5R draining the group's voltage down to where the BMB wants it to be. Still clear?
OK, now think about what happens when the pack is charging. If the bleeder resistors are turned on by the FET, instead of bleeding power out of the group, you are effectively limiting the ability for that group to charge. Not completely, the cells will still receive some of the charge current, but not as much as if the cells in the group were the only electrical path through. Remember, the charge is current-limited, so by shunting around a group, you take the available current and divide it through two paths -- one through the group, one around it. This limits the voltage available to that specific group while the others still receive their full "dose". This isn't "shuttling" of charge from one group or module to another, but it is a way to control how much each group/module charges.
Furthermore, the FET can either be turned on hard, or activated in its linear region, depending on whether the BMB's signal to the FET's gate is digital logic or analog. What this means is that the FET itself can be anything between a dead short (or close to it -- the Rds(on) spec), and open circuit. With a DAC feeding the gate, you could variably control the impedance through that bleeder circuit (fixed resistors in series with the variable FET resistance), for any one cell group, and ultimately for the entire module. This enables active control over the amount of charge of any cell group in the entire pack. Ergo, that "active impedance" thing someone spoke of earlier. Pretty clever.
